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SP5024
3-Wire Bus Controlled Synthesiser
DS2452 - 2.1 December 1992
The SP5024 is a programming variant of the SP5510 allowing the design of one tuner with either I 2C bus or 3-wire bus format depending on which device is inserted. The SP5024, when used with a TV varicap tuner, forms a complete phase locked loop tuning system. The circuit consists of a divide-by-8 prescaler with its own preamplifier and a 15 bit programmable divider controlled by a serially - loaded data register. Four open-collector outputs, each independently programmable, are included. The device has two modes of operation selected by the 'mode selected input'. In mode 1 the comparison frequency is 7.8125kHz and the programmable divider MSB is bypassed; mode 2 comparison frequency is 6.25kHz. The comparison frequencies are both obtained from a 4MHz crystal controlled on-chip oscillator. The comparator has a charge pump output with an output amplifier stage around which feedback may be applied. Only one external transistor is required for varicap line driving.
CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P4 PORT P3 PORT P2 PORT P1
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC NC NC LOCK ENABLE
FEATURES s Complete 1.3GHz Single Chip System s Dual Standard 50kHz or 62.5kHz Step Size s Low Power Consumption (5V 40mA) s Programming Compatible with Toshiba TD6380 and TD6381 * s Pin Compatible with SP5510 * s Low Radiation s Varactor Drive Amplifier Disable s Charge Pump Disable s Single Port 18/19 Bit Serial Data Entry s Four Controllable Outputs s ESD Protection
DP18
CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P4 PORT P3 PORT P2
1
16
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC LOCK ENABLE
8
9
PORT P1
MP16
* See notes on pin compatibility
Normal ESD handling procedures should be observed
Fig. 1 Pin connections - top view
APPLICATIONS s Satellite TV When Combined With SP4902 2.5GHz Prescaler s Cable Tuning Systems s VCRs
ORDERING INFORMATION
SP5024 DP SP5024S MP (18-lead plastic package) (16-lead miniature plastic package)
SP5024
ELECTRICAL CHARACTERISTICS
Tamb = -20C to +80C, VCC = +4*5V to +5*5V. Reference frequency = 4MHz. Pin numbers refer to SP5024 (DP package). These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input voltage Prescaler input impedance Input capacitance High level input voltage High level input voltage Low level input voltage High level input current Low level input current Low level input current High level input current Low level input current Clock input hysteresis Clock rate Data set up time Data hold time Enable set up time Enable hold time Clock-to-enable time Charge pump output current Charge pump output leakage current Drift due to leakage Charge pump drive output current Charge pump amplifier gain Oscillator temperature stability Oscillator stability with supply voltage Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator source impedance 2 2 10 40 -400 mV p-p Nominal spread = 615% 18 1 6400 2 2 200 ppm/C ppm/V "Parallel resonant" crystal t2 t3 t1 t5 t4 Symbol ICC Pin Min. 14 15,16 15, 16 15,16 4,5,10 3 3,4,5,10 4,5,10 5 4,10 3 3 5 5 4 4 10 10 10 1 1 300 600 300 600 300 150 5 5 0.4 0.5 3 4 0 12.5 30 50 2 VCC VCC 0.6 1 5 -250 150 -1 Typ. 40 Max. 55 300 300 mA mVRMS mVRMS pF V V V A A A A A V MHz ns ns ns ns ns A nA mV/s mA See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 4 V pin 1 = 2*0V V pin 1 = 2*0V At collector of external varicap drive transistor V pin 18 = 0*7V Pin 18 Current 100A VIN = 5*5V, VCC = 5*5V VIN = 0V, VCC = 5*5V VIN = 0V, VCC = 5*5V VIN = 5*5V, VCC = 5*5V VIN = 0V, VCC = 5*5V VCC = 5V 50MHz to 1GHz sinewave 1.3GHz, see Fig. 5 Units Conditions
2
SP5024
ELECTRICAL CHARACTERISTICS (continued)
Value Characteristic Port and Lock sink current Port leakage current Lock leakage current Varactor Drive Amp Disable Charge Pump Disable Symbol Pin Min. 6 - 9,11 6-9 11 10 4 -350 -350 10 10 10 Typ. Max. mA A A A A VOUT = 0.7V VOUT = 13.2V VOUT = VCC VIN = <0V VIN = <0V Units Conditions
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE = 0V Parameter Supply voltage Prescaler inputs Output ports Total port output current Prescaler DC offset Loop amplifier DC offset Crystal oscillator DC offset Data bus inputs Storage temperature Junction temperature DP 18 thermal resistance, chip-to-ambient DP 18 thermal resistance, chip-to-case MP 16 thermal resistance, chip-to-ambient MP 16 thermal resistance, chip-to-case Power consumption at 5V Pin Pin SP5024 SP5024 S 14 15, 16 6-9 6-9 15, 16 1, 18 2 4, 5 ,10 12 13, 14 6-9 6-9 13, 14 1, 16 2 4, 5 ,10 -0.3 -0.3 -0.3 -0.7 -55 -0.3 -0.3 Value Units Min. -0.3 Max. -6 2.5 14 6 50 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 +125 +150 78 24 111 41 275 V Vp-p V V mA V V V V C C C/W C/W C/W C/W mW All ports off With VCC applied Port in off state Port in on state Conditions
VCC RF IN RF IN
PRE AMP
48 PRESCALER
14/15 BIT PROGRAMMABLE DIVIDER
FPD
PHASE COMP F
FCOMP
4640/ 512
OSC 4MHz
CRYSTAL
CLOCK DATA ENABLE MODE SELECT DATA INPUT INTERFACE
DATA CLOCK MODE SELECT
CHARGE PUMP 14/15 BIT LATCH DIVIDER RATIO CHARGE PUMP AMP DRIVE/VARICAP OUTPUT
CONTROL OUTPUT BUFFER CPDIS VADIS
LOCK DETECT
VEE
P4 P3 P2 P1
LOCK
Fig.2 Block diagram
3
SP5024
FUNCTIONAL DESCRIPTION
The SP5024 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscillator, so forming a PLL frequency synthesised source. The system is controlled by a microprocessor via a standard data, clock, enable, three-wire data bus. The data load normally consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. The clock input is disabled during enable low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of the enable, so giving improved fine tune facility for digital AFC etc. The data sequence and timing follows the format shown in Fig. 3. The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of this divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domain to the internally generated comparison frequency, FCOMP. The FCOMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used is generally 4MHz, which gives an FCOMP of 6.25kHz/7.8125kHz and, when multiplied back up to the synthesised LO, gives a minimum step size of 50kHz/62.5kHz, respectively. The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input sensitivity and impedance are shown in Figs. 5 and 7, respectively. The SP5024 contains an improved lock detect circuit which generates a flag when the loop has attained lock. `Out of lock' is indicated by high impedance state. The SP5024 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least 10mA. These outputs are set by the remaining four bits within the normal data word.
PIN COMPATIBILITY
The SP5024 may be used in SP5510 applications which require 3-wire bus as opposed to I2C bus data format. In SP5510 applications where the reference crystal is connected to pin 3, a small modification is required to ground the crystal as shown in Fig. 4. Appropriate connections to the mode select input (pin 3) must also be made. In mode 1 (pin 3 'HIGH') the SP5024 is programming and step size compatible with the Toshiba TD6380, and in mode 2 (pin 3 'LOW') it is compatible with the TD6381. In both modes a 4MHz crystal is used to derive FCOMP, unlike the TD6381 which requires a 3.2MHz crystal.
CLOCK
CHIP ENABLE DATA MODE 1 (PIN 3 HIGH) 217
P1
216
P2
215
P3
214
P4
213
MSB
212
22
21
20
LSB
CLOCK
CHIP ENABLE
DATA t1 = ENABLE SET-UP TIME t2 = DATA SET-UP TIME t3 = DATA HOLD TIME t4 = CLOCK-TO ENABLE TIME t5 = ENABLE HOLD TIME
t1 t4 t2 t3 t5
Fig. 3 Data format and timing
4

FREQUENCY DATA (LSB = 50kHz, with 4MHz reference)
DATA MODE 2 (PIN 3 LOW)
218
P1
217
P2
216
P3
215
P4

FREQUENCY DATA (LSB = 62.5kHz, with 4MHz reference)
214
MSB
213
22
21
20
LSB
SP5024
130V 15V
22k
112V
47n 180n 10k 22k 4MHz CRYSTAL 18p 1 2 3 4 18 17 16 15 1n 1n OSCILLATOR OUTPUT 2N3904 47k 10n VARACTOR INPUT
5 SP5024 14 P4 6 7 8 9 13 12 11 10
TUNER
CONTROL MICRO
P3 P2 P1
BAND INPUTS
Fig. 4 Typical application (FSTEP = 50kHz)
300
VIN (mV RMS INTO 50 )
37.5
OPERATING WINDOW
25
12.5
500
1000 FREQUENCY (MHz)
1500
Fig. 5 Typical input sensitivity
VREF
VCC
2 x 3k
CHARGE PUMP
RF INPUTS 170 DRIVE OUTPUT
RF input
Loop amplifier
Fig.6a Input/Output interface circuits
5
SP5024
INPUT
CLOCK
Enable and data inputs
Clock input
OUTPUT
CRYSTAL
Reference oscillator
Output ports P1-P4 and Lock output
Fig.6b Input/Output interface circuits
Fig.7 Typical input impedance
6
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